The development board of Yilingsi Titanium series FPGA Ti60F255 has been released for some days. The onboard HDMI circuit is theoretically mature (I have verified it on other FPGAs), but it has not been able to squeeze out the time to transplant HDMI 1.4. , today we will challenge the IO simulation 1080P60, and make the Yilingsi Ti60 FPGA clocked at 750MHz!HDMI uses the same transmission principle as DVI - TMDS minimizes the transmission of differential signals.The TMDS transmission system is divided into two parts: the sender and the receiver.The TMDS sending end receives the 24bit RGB signal from the HDMI interface, then encodes and converts the data to parallel/serial, and then distributes the data of the RGB signal to an independent transmission channel and sends it out.The receiver receives the serial signal from the transmitter, decodes and converts it to serial/parallel, and then sends it to the display's control terminal; at the same time, it also receives the clock signal to achieve synchronization.For the design of many FPGAs on the Internet to simulate HDMI PHY, please refer to https://zhuanlan.zhihu.com/p/435937460.Among them, Digilent's HDMI IP is the most common. It uses VHDL to simulate TMDS, and uses FPGA to realize HDMI transmission and reception, which saves the cost of external PHY chips (https://github.com/Digilent/vivado-library).The Digilent HDMI IP solution has been transplanted on other platforms by many friends, and I have also tested it on Xilinx and Anlu. It is implemented in VHDL, which is a little complicated.But today I will digest and absorb another HDMI tx ip (written in Verilog, the structure is very simple) on the basis of FAE Wang Qi, 1080P60 under the challenge of Yilingsi Ti60 FPGA (in fact, the main frequency mainly depends on the rate of the transceiver) .Thanks also to the fruits of the labor of the HDMI IP creator, the Verilog Header is as follows:In addition, the key here is that we use Double Data IO of Yilingsi. The configuration is as follows. Here, both hdmi_tx_data and hdmi_tx_clk are turned on in resync mode:Query the Efinity help document, you can see the Resync Mode of DDIO, the user inputs OUT0+OUT1 on the falling edge of Clock, GPIO outputs OUT0 on the rising edge, and outputs OUT1 on the falling edge of Clock, thus achieving the purpose of frequency multiplication (HI here is OUT0 , LO is OUT1).Finally, using Efinity for synthesis, the logic in the above figure runs to 750M Hz, and DDIO achieves a bandwidth of 1.5Gbps.DDIO 1.5Gbps is already the bottleneck of Yilingsi. Although there is a little timing violation (150M to 750M cross-clock domain part of the circuit), but HDMI 1080P60 has been successfully displayed, as shown below (stole the picture from 8 years ago, too lazy to shoot) .I originally planned to transplant the LVDS mode, but the frequency could not go up. At present, it is suspected that the HDMI circuit has to be added with a pull-up resistor. The current version is omitted. I will try it again in the future.Next, go to T35 to transplant HDMI to test how much frequency it can run, at least it should be able to run 720P, right?